The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2006
Filed:
Nov. 17, 2003
Po-shou Liao, Keelung, TW;
Benny Huang, Jhonghe, TW;
Charles Lai, Taipei, TW;
Jimmy Liao, Erlin Township, TW;
Bing LI, Fremont, CA (US);
Ilya Languev, Fremont, CA (US);
Peter Eldredge, Scotts Valley, CA (US);
Leslie F. Smith, Puyallup, WA (US);
Felix Lai, Jhongjheng District, TW;
Sino Ho, Hsinchu, TW;
Ellis E-li Chang, Saratoga, CA (US);
Sandeep Bhagwat, Milpitas, CA (US);
Anthony Cheung, Milpitas, CA (US);
Michael J. Bellon, Gilroy, CA (US);
Po-Shou Liao, Keelung, TW;
Benny Huang, Jhonghe, TW;
Charles Lai, Taipei, TW;
Jimmy Liao, Erlin Township, TW;
Bing Li, Fremont, CA (US);
Ilya Languev, Fremont, CA (US);
Peter Eldredge, Scotts Valley, CA (US);
Leslie F. Smith, Puyallup, WA (US);
Felix Lai, Jhongjheng District, TW;
Sino Ho, Hsinchu, TW;
Ellis E-Li Chang, Saratoga, CA (US);
Sandeep Bhagwat, Milpitas, CA (US);
Anthony Cheung, Milpitas, CA (US);
Michael J. Bellon, Gilroy, CA (US);
KLA-Tencor Technologies Corporation, Milpitas, CA (US);
Abstract
An extensible data analysis system for analyzing integrated circuit fabrication data produced during integrated circuit fabrication, including an application tier that selectively runs analysis nodes. The application tier has an architecture for optionally including and excluding a desired selection of the analysis nodes. The application tier architecture allows the selection of the analysis nodes to be dynamically added by a user. A data access tier selectively runs data reader nodes. The data access tier has an architecture for optionally including and excluding a desired selection of the data reader nodes. The data reader nodes interpret a desired variety of data source files containing the integrated circuit fabrication data having different formats for access by the application tier. The data access tier architecture allows the selection of the data reader nodes to be dynamically added by the user.