The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2006
Filed:
Mar. 19, 2004
Applicants:
N. Johan Knall, Sunnyvale, CA (US);
Mark Johnson, Los Altos, CA (US);
Inventors:
N. Johan Knall, Sunnyvale, CA (US);
Mark Johnson, Los Altos, CA (US);
Assignee:
Sandisk 3D LLC, Milpitas, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
Abstract
A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.
Knall, N.. (2006). Three-dimensional memory array and method of fabrication (U.S. Patent No. 7091529). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7091529
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile