The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2006
Filed:
Apr. 11, 2003
Sang Hyeon Baeg, Cupertino, CA (US);
Sung Soo Chung, San Jose, CA (US);
Hongshin Jun, San Jose, CA (US);
Sang Hyeon Baeg, Cupertino, CA (US);
Sung Soo Chung, San Jose, CA (US);
Hongshin Jun, San Jose, CA (US);
Cisco Technology, Inc., San Jose, CA (US);
Abstract
Programmable test pattern driver and capture mechanisms for boundary scan cluster or functional block testing. A boundary scan test system includes at least one device under test. The device may include a Test Access Port (TAP) controller, a plurality of output AC boundary scan cells (BSCs), and a plurality of input AC BSCs. The device may further include a programmable AC_Pattern_Source signal generator configured to produce AC signal patterns that selectively remain unchanged for at least one cycle before and after an original capture cycle location, a programmable AC_Sync signal generator configured to independently control the AC_Sync signal to lead or lag an original cycle location at full cycle increments, a programmable phase controller configured to independently control either the rising or falling edge aligned AC_Pattern_Clock signal or AC_Counter_Clock signal, and an AC_Test_Clock signal switcher configured to selectively utilize one of a plurality of clock signals including a TCK signal.