The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2006

Filed:

Aug. 16, 2004
Applicants:

Aik Koon Loh, Singapore, SG;

Keen Fung Wai, Singapore, SG;

Tiam Hock Tan, Singapore, SG;

Roy H. Williams, Loveland, CO (US);

Daniel Z. Whang, Singapore, SG;

Chen NI Low, Singapore, SG;

Ellis Yuan, Pingzhen, TW;

Inventors:

Aik Koon Loh, Singapore, SG;

Keen Fung Wai, Singapore, SG;

Tiam Hock Tan, Singapore, SG;

Roy H. Williams, Loveland, CO (US);

Daniel Z. Whang, Singapore, SG;

Chen Ni Low, Singapore, SG;

Ellis Yuan, Pingzhen, TW;

Assignee:

Agilent Technologies, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for configuring an automated in-circuit test debugger is presented. The novel test debug and optimization configuration technique configures expert knowledge into a knowledge framework for use by an automated test debug and optimization system for automating the formulation of a valid stable in-circuit test for execution on an integrated circuit tester. In a system that includes a rule-based controller for controlling interaction between the test-head controller of an integrated circuit tester and an automated debug system, the invention includes a knowledge framework and a rule-based editor. The knowledge framework stores test knowledge in the representation of rules that represent a debugging strategy. The rule-based editor facilitates the use of rules as knowledge to debug or optimize an in-circuit test that is to be executed on the integrated circuit tester.


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