The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2006
Filed:
Nov. 06, 2003
Applicants:
OM P. Agrawal, Los Altos, CA (US);
Jason Cheng, Fremont, CA (US);
Paul R. Bonwick, Corsham, GB;
Bradley Felton, Corsham, GB;
Andrew Armitage, Corsham, GB;
Inventors:
Om P. Agrawal, Los Altos, CA (US);
Jason Cheng, Fremont, CA (US);
Paul R. Bonwick, Corsham, GB;
Bradley Felton, Corsham, GB;
Andrew Armitage, Corsham, GB;
Assignee:
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/01 (2006.01);
U.S. Cl.
CPC ...
Abstract
A programmable logic device includes a plurality of logic blocks organized into a cluster. Each logic block may be configured into a logic mode and a memory mode. The logic blocks are arranged into at least one cluster, each cluster having a data bus configured to provide data words to logic blocks within its cluster.