The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7088131 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 08, 2006

Filed:

Jul. 29, 2005
Applicants:

Douglas W. Stout, Milton, VT (US);

Charles H. Windisch, Jr., Essex Junction, VT (US);

Inventors:

Douglas W. Stout, Milton, VT (US);

Charles H. Windisch, Jr., Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01); G05F 3/02 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Power is gated from global terrain to a voltage island while controlling leakage and managing transient power supply noise. The voltage island includes a field effect transistor (FET) power gate, a first connection to a global voltage source and a second connection to a disable signal source, and an island voltage net for supplying voltage to devices on the island. A power gate control circuit is responsive to the disable signal source for generating a test signal for selectively turning off the FET power gate as the disable signal source goes to a logical '1', and for turning on the FET power gate as said disable source goes to a logical '0'. The FET power gate is responsive to the disable signal source being off for connecting the island voltage net to the global voltage source. A turn on finisher circuit is responsive to the disable signal transitioning to on and to the test signal for holding the power gate solidly on; and a turn off finisher circuit is responsive to the disable signal transitioning to off and to the test signal for holding said power gate solidly off.


Find Patent Forward Citations

Stout, Douglas. (2006). System and method for power gating (U.S. Patent No. 7088131). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7088131

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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