The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2006
Filed:
Aug. 18, 2004
Muhammed Ayman Shibib, Wyomissing, PA (US);
Shuming Xu, Schnecksville, PA (US);
Muhammed Ayman Shibib, Wyomissing, PA (US);
Shuming Xu, Schnecksville, PA (US);
Agere Systems Inc., Allentown, PA (US);
Abstract
An MOS device includes a semiconductor layer formed on a substrate, the substrate defining a horizontal plane and a vertical direction normal to the horizontal plane. First and second source/drain regions are formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A gate is formed proximate the upper surface of the semiconductor layer and disposed at least partially between the first and second source/drain regions. A first dielectric region is formed in the MOS device, the first dielectric region defining a trench extending downward from the upper surface of the semiconductor layer to a first distance into the semiconductor layer, the first dielectric region being formed between the first and second source/drain regions. The MOS device further includes a shielding structure formed primarily in the first dielectric region, at least a portion of the shielding structure being disposed adjacent a bottom wall of the first dielectric region and/or one or more sidewalls of the first dielectric region.