The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2006
Filed:
Dec. 20, 2002
Jed H. Rankin, Richmond, VT (US);
Wagdi W. Abadeer, Jericho, VT (US);
Jeffrey S. Brown, Middlesex, VT (US);
William R. Tonti, Essex Junction, VT (US);
Jed H. Rankin, Richmond, VT (US);
Wagdi W. Abadeer, Jericho, VT (US);
Jeffrey S. Brown, Middlesex, VT (US);
William R. Tonti, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method is described for fabricating and antifuse structure () integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material () is provided overlying an insulator () disposed on a substrate (); an etching process exposes a plurality of corners () in the semiconducting material. The exposed corners are oxidized to form elongated tips () at the corners; the oxide () overlying the tips is removed. An oxide layer (), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material () is formed in contact with the oxide layer () at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path ().