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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7085935 B1

PDFFull Text
Date of Patent:
Aug. 01, 2006

Filed:

Sep. 22, 2000

Managing a secure environment using a chipset in isolated execution mode

Applicants:

Carl M. Ellison, Portland, OR (US);

Roger A. Golliver, Beaverton, OR (US);

Howard C. Herbert, Phoenix, AZ (US);

Derrick C. Lin, San Mateo, CA (US);

Francis X. Mckeen, Portland, OR (US);

Gilbert Neiger, Portland, OR (US);

Ken Reneris, Wilbraham, MA (US);

James A. Sutton, Portland, OR (US);

Shreekant S. Thakkar, Portland, OR (US);

Millind Mittal, Palo Alto, CA (US);

Inventors:

Carl M. Ellison, Portland, OR (US);

Roger A. Golliver, Beaverton, OR (US);

Howard C. Herbert, Phoenix, AZ (US);

Derrick C. Lin, San Mateo, CA (US);

Francis X. McKeen, Portland, OR (US);

Gilbert Neiger, Portland, OR (US);

Ken Reneris, Wilbraham, MA (US);

James A. Sutton, Portland, OR (US);

Shreekant S. Thakkar, Portland, OR (US);

Millind Mittal, Palo Alto, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Michael R. Barre

Primary Examiner:

Ayaz Sheikh

Assistant Examiner:

Taghi T Arani

Int. Cl.
CPC ...
G08F 13/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

A chipset is initialized in a secure environment for an isolated execution mode by an initialization storage. The secure environment has a plurality of executive entities and is associated with an isolated memory area accessible by at least one processor. The at least one processor has a plurality of threads and operates in one of a normal execution mode and the isolated execution mode. The executive entities include a processor executive (PE) handler. PE handler data corresponding to the PE handler are stored in a PE handler storage. The PE handler data include a PE handler image to be loaded into the isolated memory area after the chipset is initialized. The loaded PE handler image corresponds to the PE handler.

Find Patent Forward Citations

Quick Actions:

Ellison, Carl. (2006). Managing a secure environment using a chipset in isolated execution mode (U.S. Patent No. 7085935). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7085935

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