The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2006
Filed:
Jun. 23, 2003
Norio Ishitsuka, Chiyoda, JP;
Tomio Iwasaki, Tsukuba, JP;
Hiroyuki Ohta, Tsuchiura, JP;
Hideo Miura, Sendai, JP;
Masahito Takahashi, Tachikawa, JP;
Norio Suzuki, Mito, JP;
Shuji Ikeda, Koganei, JP;
Hideki Tanaka, Chino, JP;
Hiroyuki Mima, Hitachinaka, JP;
Norio Ishitsuka, Chiyoda, JP;
Tomio Iwasaki, Tsukuba, JP;
Hiroyuki Ohta, Tsuchiura, JP;
Hideo Miura, Sendai, JP;
Masahito Takahashi, Tachikawa, JP;
Norio Suzuki, Mito, JP;
Shuji Ikeda, Koganei, JP;
Hideki Tanaka, Chino, JP;
Hiroyuki Mima, Hitachinaka, JP;
Hitachi, Ltd., Tokyo, JP;
Trecenti Technologies, Inc., Hitachinaka, JP;
Abstract
To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.