The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2006
Filed:
Feb. 26, 2004
Puneet Gupta, LaJolla, CA (US);
Fook-luen Heng, Yorktown Heights, NY (US);
David S. Kung, Chappaqua, NY (US);
Daniel L. Ostapko, Mahopac, NY (US);
Puneet Gupta, LaJolla, CA (US);
Fook-Luen Heng, Yorktown Heights, NY (US);
David S. Kung, Chappaqua, NY (US);
Daniel L. Ostapko, Mahopac, NY (US);
International Business Machines Corp., Armonk, NY (US);
Abstract
An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.