Polymer memory having a ferroelectric polymer memory material with cell sizes that are asymmetric

Abstract

A polymer memory and its method of manufacture are provided. One multi-layer construction of the polymer memory has two sets of word lines and a set of bit lines between the word lines. The word lines of each set of word lines have center lines that are spaced by a first distance from one another, and the bit lines have center lines spaced by a second distance from one another, the second distance being less than the first distance. Three masking steps are required to manufacture the three layers of lines. Older-technology machinery and masks are used to form the two layers of word lines, and new-technology machinery and masks are used to manufacture the bit lines. As such, only 33% of the machinery has to be upgraded for manufacturing one multi-layer construction. The entire polymer memory has four multi-layer constructions having a total of 12 layers of lines, of which four layers require new-technology machinery. The multi-layer constructions are formed on underlying electronics. The underlying electronics are constructed utilizing 28 masking steps, 4 of the 28 masking steps requiring new-technology machinery. As such, the manufacture of the entire polymer memory requires 40 masking steps, 8 of which require new-technology machinery. A 20% machinery upgrade is thus required for manufacturing the entire polymer memory, which is generally regarded as acceptable when upgrading machinery from one generation to the next.