The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2006

Filed:

Mar. 12, 2004
Applicants:

Min-chul Sun, Busan, KR;

Ja-hum Ku, Seongnam, KR;

Sug-woo Jung, Suwon, KR;

Sun-pil Youn, Seoul, KR;

Min-joo Kim, Seoul, KR;

Kwan-jong Roh, Anyang, KR;

Inventors:

Min-Chul Sun, Busan, KR;

Ja-Hum Ku, Seongnam, KR;

Sug-Woo Jung, Suwon, KR;

Sun-Pil Youn, Seoul, KR;

Min-Joo Kim, Seoul, KR;

Kwan-Jong Roh, Anyang, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of fabricating a semiconductor device having a MOS transistor with a strained channel are provided. The method includes forming a MOS transistor at a portion of a semiconductor substrate. The MOS transistor is formed to have source/drain regions spaced apart from each other and a gate electrode located over a channel region between the source/drain regions. A stress layer is formed on the semiconductor substrate having the MOS transistor. The stress layer is then annealed to convert a physical stress of the stress layer into a tensile stress or increase a tensile stress of the stress layer.


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