The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2006
Filed:
Mar. 05, 2004
Albert Birner, Dresden, DE;
Steffen Breuer, Heiddorf, DE;
Matthias Goldbach, Dresden, DE;
Joern Luetzen, Dresden, DE;
Dirk Schumann, Schoenfliess, DE;
Albert Birner, Dresden, DE;
Steffen Breuer, Heiddorf, DE;
Matthias Goldbach, Dresden, DE;
Joern Luetzen, Dresden, DE;
Dirk Schumann, Schoenfliess, DE;
Infineon Technologies AG, Munich, DE;
Abstract
A method for producing a silicon-on-insulator layer structure on a silicon surface with any desired geometry can locally produce the silicon-on-insulator structure. The method includes formation of mesopores in the silicon surface region, oxidation of the mesopore surface to form silicon oxide and rib regions from silicon in single-crystal form; and execution of a selective epitaxy process that that silicon grows on the uncovered rib regions, selectively with respect to the silicon oxide regions. Rib regions remain in place between adjacent mesopores, this step being ended as soon as a predetermined minimum silicon wall thickness of the rib regions is reached, the uncovering of the rib regions, which are arranged at the end remote from the semiconductor substrate between adjacent mesopores. The method can be used to fabricate a vertical transistor and a memory cell having a select transistor of this type.