The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2006

Filed:

Nov. 26, 2003
Applicants:

David Goren, Nesher, IL;

Rachel Gordin, Hadera, IL;

Michael Zelikson, Haifa, IL;

Inventors:

David Goren, Nesher, IL;

Rachel Gordin, Hadera, IL;

Michael Zelikson, Haifa, IL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a systemfor designing an integrated circuit, a preliminary design of the integrated circuit is defined and critical interconnect lines in the preliminary design are identified. Further, any critical interconnect lines which are affected by crossing lines in the preliminary design are identified, and a transmission line modelis defined to represent each critical interconnect line. A layout design of the integrated circuit, comprising circuit components and parameters thereof, is then defined using the preliminary design and the transmission line modelfor each critical interconnect line. Component parameters are then extracted from the layout design for simulation of the design using the extracted component parameters. During this design process, for each transmission line modelrepresenting a critical interconnect line affected by a crossing line, an environment terminalis provided. The environment terminalcomprises a connection to the modelvia at least one circuit component representing the effect of the crossing line on the model. The environment terminalis connected to the appropriate crossing line in the integrated circuit design, whereby crossing line effects are accommodated in the design process.


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