The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2006
Filed:
Jun. 18, 2004
John M. Cohn, Richmond, VT (US);
Leah Marie P. Pastel, Essex, VT (US);
Thomas G. Sopchak, Williston, VT (US);
David P. Vallett, Fairfax, VT (US);
John M. Cohn, Richmond, VT (US);
Leah Marie P. Pastel, Essex, VT (US);
Thomas G. Sopchak, Williston, VT (US);
David P. Vallett, Fairfax, VT (US);
International Business machines Corporation, Armonk, NY (US);
Abstract
A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first wire in each of the first plurality of wire pairs is electrically coupled to conductive structures beneath the first metal interconnect level, and a second wire in each of the first plurality of wire pairs is initially electrically isolated from the conductive structures beneath the first metal interconnect level. The first wire in each of the first plurality of wire pairs is biased to a known voltage, and a charge contrast inspection is performed between the first wire and the second wire of each of the first plurality of wire pairs.