The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7076750 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 11, 2006

Filed:

Feb. 06, 2001
Applicant:

Todd P. Lukanc, San Jose, CA (US);

Inventor:

Todd P. Lukanc, San Jose, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of checking a computer generated circuit layout involves selecting vias with at least an edge coincident to an edge of a metal line. Once vias are selected, based upon whether a via touches an edge of a metal line, information regarding the distance between metal lines is determined. Metal lines are resized in the vicinity of a via with an edge touching an edge of a metal line in order to effect a complete connection between the metal line and the via in a manufactured integrated circuit taking into account the information regarding the distance between metal lines. Resized metal lines do not impact metal lines adjacent to the edge that a via was touching because adjacent metal lines are resized to account for a too small separation distance if necessary.


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Lukanc, Todd. (2006). Method and apparatus for generating trenches for vias (U.S. Patent No. 7076750). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7076750

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