The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2006

Filed:

May. 28, 2004
Applicants:

Douglas W. Kemerer, Essex Junction, VT (US);

Daniel N. Maynard, Craftsbury Common, VT (US);

Gustavo E. Tellez, Essex Junction, VT (US);

Lijiang L. Wang, South Burlington, VT (US);

Peter S. Wissell, Cambridge, VT (US);

Inventors:

Douglas W. Kemerer, Essex Junction, VT (US);

Daniel N. Maynard, Craftsbury Common, VT (US);

Gustavo E. Tellez, Essex Junction, VT (US);

Lijiang L. Wang, South Burlington, VT (US);

Peter S. Wissell, Cambridge, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and a system for improving manufacturing productivity of an integrated circuit. The method including: (a) generating a set of physical design rules, (b) assigning a rule scoring equation to each physical design rule of the set of physical design rules; (c) checking a physical design of the integrated circuit for deviations from each design rule; (d) computing a score for each physical design rule, using the corresponding rule scoring equation assigned to each physical design rule, for which one or more deviations were found in step (c); and (e) computing a productivity score for the integrated circuit design based on the scores computed in step (d).


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