The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2006
Filed:
Apr. 28, 2000
Michael J. Demler, Scotts Valley, CA (US);
Stephen Lim, Scotts Valley, CA (US);
Geoffrey Ellis, Santa Cruz, CA (US);
Leslie D. Spruiell, Santa Clara, CA (US);
Robert W. Mcguffin, Felton, CA (US);
Bent H. Sorensen, Le Vaud, CH;
Michael J. Demler, Scotts Valley, CA (US);
Stephen Lim, Scotts Valley, CA (US);
Geoffrey Ellis, Santa Cruz, CA (US);
Leslie D. Spruiell, Santa Clara, CA (US);
Robert W. McGuffin, Felton, CA (US);
Bent H. Sorensen, Le Vaud, CH;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Circuit synthesis is performed utilizing an optimizer that selects design parameters for a synthesis model of a circuit based on desired performance characteristics and performance characteristics/design parameters of previously synthesized circuits. Performance characteristics and design parameters of each synthesized circuit are maintain in conjunction with the synthesis model of the circuit being synthesized. A synthesis plan identifies the synthesis model and specific instructions on how to perform optimized selection of design parameters, how to set up test benches, and how to perform the simulation.