The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2006

Filed:

Mar. 12, 2003
Applicants:

Kate E. Fey, Valenica, CA (US);

Charles L. Byers, Canyon Country, CA (US);

Lee J. Mandell, West Hills, CA (US);

Inventors:

Kate E. Fey, Valenica, CA (US);

Charles L. Byers, Canyon Country, CA (US);

Lee J. Mandell, West Hills, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus and packaging method for stacking a plurality of integrated circuit substrates, i.e., substrates having integrated circuits formed as integral portions of the substrates, which provides interconnection paths through the substrates to simplify electrical connections between the integrated circuits while facilitating minimization of the volume and customization of the three dimensional package size to conform to the available internal space within a housing, e.g., one used in an implantabie device where package volume is at a premium. Furthermore, an internal cavity can be created by the stacked formation that is suitable for mounting of a surface mount device, e.g., a crystal or the like.

Published as:
WO03063242A1; US2003192171A1; EP1472730A1; US7071546B2; EP1472730A4;

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