The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2006

Filed:

Apr. 23, 2003
Applicants:

Christy Woo, Cupertino, CA (US);

Paul Besser, Sunnyvale, CA (US);

Minh Van Ngo, Fremont, CA (US);

James Pan, Santa Clara, CA (US);

Jinsong Yin, Sunnyvale, CA (US);

Inventors:

Christy Woo, Cupertino, CA (US);

Paul Besser, Sunnyvale, CA (US);

Minh van Ngo, Fremont, CA (US);

James Pan, Santa Clara, CA (US);

Jinsong Yin, Sunnyvale, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming a semiconductor structure having a metal gate with a controlled work function includes the step of forming a precursor having a substrate with active regions separated by a channel, a temporary gate over the channel and within a dielectric layer. The temporary gate is removed to form a recess with a bottom and sidewalls in the dielectric layer. A non-silicon containing metal layer is deposited in the recess. Silicon is incorporated into the metal layer and a metal is deposited on the metal layer. The incorporation of the silicon is achieved by silane treatments that are performed before, after or both before and after the depositing of the metal layer. The amount of silicon incorporated into the metal layer controls the work function of the metal gate that is formed.


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