The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 27, 2006

Filed:

May. 28, 2004
Applicants:

Gene T. Sluss, Pleasanton, CA (US);

Deepak D. Sherlekar, Cupertino, CA (US);

Tushar R. Gheewala, Los Altos, CA (US);

Inventors:

Gene T. Sluss, Pleasanton, CA (US);

Deepak D. Sherlekar, Cupertino, CA (US);

Tushar R. Gheewala, Los Altos, CA (US);

Assignee:

Virage Logic Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Various methods and apparatuses are described in which a volatile latch circuit. The volatile latch circuit may have a master latch sub circuit coupled to a slave latch sub circuit. The slave latch sub circuit maintains the logic state stored by the volatile latch circuit. The slave sub circuit may connect to a first power trace that continuously provides a first voltage potential to the slave latch sub circuit even during a sleep mode. The master latch sub circuit may connect to a second power trace that provides a second voltage potential to the master latch sub circuit that is switchably turned off during the sleep mode.


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