Multi-bank content addressable memory (cam) devices having staged segment-to-segment soft and hard priority resolution circuits therein and methods of operating same

Abstract

Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devices include priority resolution circuits that can resolve competing soft and hard priorities between multiple hit signals that are generated in response to a search operation. Such hit signals may be active to reflect the presence of at least one matching entry within a CAM array block. The resolution of which active hit signal has the highest overall priority among many can be used to facilitate the identification of the location (e.g., array address and row address) of a highest priority matching entry within the entire CAM device. A priority resolution circuit may also resolve competing hard priorities between two or more active hit signals having equivalent soft priority.