The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2006
Filed:
Sep. 29, 2004
Lu'ay Bakir, Bolton Valley, VT (US);
Ciaran J. Brennan, Essex Junction, VT (US);
Joseph N. Kozhaya, Essex Junction, VT (US);
Robert A. Proctor, South Burlington, VT (US);
Lu'ay Bakir, Bolton Valley, VT (US);
Ciaran J. Brennan, Essex Junction, VT (US);
Joseph N. Kozhaya, Essex Junction, VT (US);
Robert A. Proctor, South Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for placing electrostatic discharge clamps within integrated circuit devices is disclosed. A region is initially defined within an integrated circuit design. A list of ESD-susceptible circuits located within the defined region is then generated. The center of gravity of the ESD-susceptible circuits located within the defined region is located. Next, an ESD protection device is placed at the center of gravity of the ESD-susceptible circuits located within the defined region. A determination is made as to whether or not all ESD-susceptible circuits within the list of ESD-susceptible circuits are protected by the placement of the ESD protection device. If so, the process is repeated in other regions until the entire integrated circuit is addressed. Otherwise, the defined region is divided into at least two smaller regions and the process is repeated.