The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2006
Filed:
Jan. 14, 2004
Applicants:
Senol Pekin, San Jose, CA (US);
Atila Mertol, Cupertino, CA (US);
Wilson Choi, San Jose, CA (US);
Inventors:
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method of optimizing a bond out design includes steps of: (a) receiving as input an initial bond out design including at least one selected I/O pad and a top redistribution layer; (b) determining whether to include a lower redistribution layer in an optimized bond out design; (c) selecting a trace design to be included in the optimized bond out design for connecting the selected I/O pad to the top redistribution layer according to a bump function of the selected I/O pad; and (d) generating as output the optimized bond out design.