The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 2006

Filed:

Sep. 16, 2004
Applicants:

Eun-mi Lee, Gyeonggi-do, KR;

Doo-hoon Goo, Gyeonggi-do, KR;

Jung-hyeon Lee, Gyeonggi-do, KR;

Gi-sung Yeo, Seoul, KR;

Inventors:

Eun-Mi Lee, Gyeonggi-do, KR;

Doo-Hoon Goo, Gyeonggi-do, KR;

Jung-Hyeon Lee, Gyeonggi-do, KR;

Gi-Sung Yeo, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

Embodiments of the invention provide methods of forming SAC pads in non-straight semiconductor device having non-straight type or separate type active regions. A plurality of gate line structures extending in one direction may be formed on a semiconductor substrate having non-straight active regions. An interlayer insulating layer covering gate line structures may be formed on the gate line structures. Then, a photo-resist layer may be formed on the interlayer insulating layer. A photo-resist pattern may be formed through exposing and developing the photo-resist layer by using a photo-mask having, for example, a bar type, a wave type, or a reverse active type pattern. Then, contact holes exposing source/drain regions may be formed by etching the interlayer insulating layer using the photo-resist pattern as an etching mask. Contact pads may then be formed by filling the contact holes with a conductive material.


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