The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2006
Filed:
Jun. 27, 2003
Takashi Miwa, Fussa, JP;
Yasumi Tsutsumi, Higashiyamato, JP;
Masahiro Ichitani, Kodaira, JP;
Takanori Hashizume, Higashiyamato, JP;
Masamichi Sato, Hachioji, JP;
Naozumi Morino, Higashiyamato, JP;
Atsushi Nakamura, Tachikawa, JP;
Saneaki Tamaki, Kodaira, JP;
Ikuo Kudo, Koganei, JP;
Takashi Miwa, Fussa, JP;
Yasumi Tsutsumi, Higashiyamato, JP;
Masahiro Ichitani, Kodaira, JP;
Takanori Hashizume, Higashiyamato, JP;
Masamichi Sato, Hachioji, JP;
Naozumi Morino, Higashiyamato, JP;
Atsushi Nakamura, Tachikawa, JP;
Saneaki Tamaki, Kodaira, JP;
Ikuo Kudo, Koganei, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.