The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2006
Filed:
Jun. 25, 2003
Kenneth A. Bandy, Red Hook, NY (US);
Vincent J. Carlos, Essex Town, VT (US);
Mark D. Levy, Essex Junction, VT (US);
Sara L. Lucas, Burlington, VT (US);
Timothy C. Milmore, South Burlington, VT (US);
Matthew C. Nicholls, South Burlington, VT (US);
Jason Nowakowski, Poughkeepsie, NY (US);
Kenneth A. Bandy, Red Hook, NY (US);
Vincent J. Carlos, Essex Town, VT (US);
Mark D. Levy, Essex Junction, VT (US);
Sara L. Lucas, Burlington, VT (US);
Timothy C. Milmore, South Burlington, VT (US);
Matthew C. Nicholls, South Burlington, VT (US);
Jason Nowakowski, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for forming a semiconductor wafer comprising of applying a first patterned resist to at least one first predetermined region of a wafer where said at least one first predetermined region of said wafer are protected by said first patterned resist and a first remaining portion of said wafer is not protected by said first patterned resist; etching said first remaining portion of said wafer not protected by said first pattern resist; stripping the first pattern resist from said wafer; applying a second patterned resist to at least one second pre-determined region of said wafer where said at least one second predetermined region of said wafer are protected by a second patterned resist and a second remaining portion is not protected by said second patterned resist; etching said second remaining portion not protected by said second patterned resist; and stripping said second patterned resist from said wafer.