The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2006
Filed:
Aug. 13, 2003
Panayotis Andricacos, Croton on Hudson, NY (US);
Emanuel Israel Cooper, Scarsdale, NY (US);
Timothy Joseph Dalton, Ridgefield, CT (US);
Hariklia Deligianni, Tenafly, NJ (US);
Daniel Guidotti, Atlanta, GA (US);
Keith Thomas Kwietniak, Highland Falls, NY (US);
Michelle Leigh Steen, Danbury, CT (US);
Cornelia Kang-i Tsang, Mohegan Lake, NY (US);
Panayotis Andricacos, Croton on Hudson, NY (US);
Emanuel Israel Cooper, Scarsdale, NY (US);
Timothy Joseph Dalton, Ridgefield, CT (US);
Hariklia Deligianni, Tenafly, NJ (US);
Daniel Guidotti, Atlanta, GA (US);
Keith Thomas Kwietniak, Highland Falls, NY (US);
Michelle Leigh Steen, Danbury, CT (US);
Cornelia Kang-I Tsang, Mohegan Lake, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.