The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2006
Filed:
Sep. 30, 2004
Geum-jong Bae, Suwon, KR;
Nae-in Lee, Seoul, KR;
Sang Su Kim, Suwon, KR;
Ki Chul Kim, Suwon, KR;
Jin-hee Kim, Seong-Nam, KR;
In-wook Cho, Yong-In, KR;
Sung-ho Kim, O-San, KR;
Kwang-wook Koh, Seong-Nam, KR;
Geum-Jong Bae, Suwon, KR;
Nae-In Lee, Seoul, KR;
Sang Su Kim, Suwon, KR;
Ki Chul Kim, Suwon, KR;
Jin-Hee Kim, Seong-Nam, KR;
In-Wook Cho, Yong-In, KR;
Sung-Ho Kim, O-San, KR;
Kwang-Wook Koh, Seong-Nam, KR;
Samsung Electronics Co., Ltd., Kyungki-Do, KR;
Abstract
A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the first gate layer and on the gate insulator. The first and second gate layers are electrically connected together. Together, the ONO structure and first and second gate layers define at least a 1-bit local SONOS structure. A corresponding method of manufacture includes: providing a substrate; forming an ONO structure on the substrate; forming a first gate layer on and aligned with the ONO structure; forming a gate insulator on the substrate aside the ONO structure; forming a second gate layer on the first gate layer and on the gate insulator; and electrically connecting the first and second gate layers.