The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 13, 2006

Filed:

Jan. 28, 2003
Applicants:

Yoshio Ozawa, Yokohama, JP;

Katsuhiko Hieda, Yokohama, JP;

Atsuko Kawasaki, Yokohama, JP;

Inventors:

Yoshio Ozawa, Yokohama, JP;

Katsuhiko Hieda, Yokohama, JP;

Atsuko Kawasaki, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a method of manufacturing a semiconductor device having a nonvolatile semiconductor memory element with a two-layered gate structure in which a floating gate and control gate are stacked, a polysilicon layer serving as the floating gate is stacked on a silicon substrate via a tunnel insulating film. Then, the silicon layer, tunnel insulating film, and substrate are selectively etched to form an element isolation trench. A nitride film is formed on the sidewall surface of the silicon layer exposed into the element isolation trench. An oxide film is buried in the element isolation trench. A conductive film serving as the control gate is stacked on the oxide film and silicon layer via an electrode insulating film. The conductive film, electrode insulating film, and silicon layer are selectively etched to form the control gate and floating gate.


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