The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2006
Filed:
Mar. 19, 2003
Sang Hoo Dhong, Austin, TX (US);
Silvia Melitta Mueller, St. Ingbert, DE;
Hwa-joon OH, Austin, TX (US);
Kevin Duc Tran, Austin, TX (US);
Sang Hoo Dhong, Austin, TX (US);
Silvia Melitta Mueller, St. Ingbert, DE;
Hwa-Joon Oh, Austin, TX (US);
Kevin Duc Tran, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention provides for saving power in a floating point unit. Bypass logic is coupled to the input of the aligner and the multiplier. An aligner bypass is coupled to the output of the aligner and an output of the bypass logic. A multiplier bypass is coupled to the output of the multiplier and an output of the bypass logic. The aligner bypass and the multiplier bypass transmit the output of the aligner and multiplier, or the bypass logic, as a function of an aligner bypass signal and a multiplier bypass signal, respectively. An adder is coupled to the output of the aligner bypass and the multiplier bypass. Clock disable logic is used to selectively enable and disable at least portions of the aligner, multiplier and bypass logic. This is done based on the operation and on the value of the operands.