The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2006
Filed:
Feb. 12, 2004
Gordon Edward Chenoweth, Portland, OR (US);
Marc P. Loranger, Livermore, CA (US);
Steven Robert Payne, Hillsboro, OR (US);
James Kaylor Larson, Portland, OR (US);
Patricia Renee Justice, Portland, OR (US);
Gordon Edward Chenoweth, Portland, OR (US);
Marc P. Loranger, Livermore, CA (US);
Steven Robert Payne, Hillsboro, OR (US);
James Kaylor Larson, Portland, OR (US);
Patricia Renee Justice, Portland, OR (US);
Credence Systems Corporation, Milpitas, CA (US);
Abstract
A system for testing an integrated circuit device under test (DUT) communicating though synchronous digital signals and through a high speed serialization/de-serialization (serdes) bus includes a serdes interface circuit for communicating with the DUT via the serdes bus and an integrated circuit (IC) tester for communicating with the DUT and with the serdes interface circuit via digital signals. State changes in the digital signals are synchronized to a clock signal within the IC tester. The serdes interface circuit receives instructions from the IC tester via at least one of the digital signals and responds to the instructions by transmitting data to the DUT via the serdes bus using appropriate serdes protocol, by receiving and storing data transmitted by the DUT via the serdes bus, and by thereafter forwarding the stored data to the IC tester via at least one of the digital signals.