The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2006
Filed:
Apr. 05, 2002
Alex Tain, Milpitas, CA (US);
Eric Tosaya, Fremont, CA (US);
Alex Tain, Milpitas, CA (US);
Eric Tosaya, Fremont, CA (US);
Cisco Technology, Inc., San Jose, CA (US);
Abstract
A method for logically connecting at least one of a plurality of top side conductors of an integrated circuit package with at least one of a plurality of bottom side conductors of the integrated circuit package. The method includes drawing a layout of the bottom side conductors, and drawing a layout of the top side conductors. One or more rings of the top side conductors are defined, and one or more rings of the bottom side conductors are defined. One or more signal sets of the top side conductors are defined, each of said signal sets contains at least two or more top side conductors. The user can select a region of top side conductors to be connected with a region of bottom side conductors, and the selected region of top side conductors is automatically connected with the selected region of bottom side conductors while maintaining the signal set relations. In this manner, the logical connection between the top and bottom side conductors of an integrated circuit package are automatically connected while maintaining the relationship between the signal sets defined by the user. A netlist can be generated of the logical connections made by the connecting operation.