The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2006
Filed:
Sep. 13, 2000
Dean S. Susnow, Portland, OR (US);
Richard D. Reohr, Jr., Hillsboro, OR (US);
Dean S. Susnow, Portland, OR (US);
Richard D. Reohr, Jr., Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A technique for de-skewing a group of serial data signals respectively outputted from a group of data lanes includes simultaneously feeding a test signal to inputs of the group of data lanes and monitoring respective outputs thereof. A predetermined data element of the test signal outputted from each of the group of data lanes is respectively detected and respective elapsed times from the detection of the predetermined data element outputted from each of the group of data lanes to the detection that the predetermined data element has been outputted from all of the group of data lanes are measured. The group of serial data signals are then de-skewed by respectively delaying them in accordance with their respective measured elapsed times. The test signal may include the predetermined data element, a lane identifier, and a predetermined number of additional data symbols, the predetermined data element being a predetermined data character. The elapsed times may be measured by a group of lane tolerance counters, each counter initiating counting upon the detection of the predetermined data element in its data lane and each counter stopping counting upon the detection that the predetermined data element has been outputted from all of the group of data lanes. The group of serial data signals may be respectively delayed by a group of registers and the amount of delay of each data signal may be selected by a respective multiplexer connected to the group of registers, each multiplexer being controlled by its' respective counter.