The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2006
Filed:
Nov. 20, 2002
Terence M. Potter, Austin, TX (US);
James S. Blomgren, Austin, TX (US);
Terence M. Potter, Austin, TX (US);
James S. Blomgren, Austin, TX (US);
Intrinsity, Inc., Austin, TX (US);
Abstract
Power consumption in NDL designs utilizing FAST14 technology can be controlled via the introduction and propagation of null value 1-of-N signals in selected areas of the logic. A shared logic tree circuit, which might perform an arithmetic function or a multiplexing function, evaluates a 1-of-N input logic signal and produces a 1-of-N output logic signal having a null value if the input has a null value. A null value signal is defined as a valid multiwire 1-of-N signal used in NDL logic having N wires where N is greater than 2, where no one of the N wires of the 1-of-N signal is asserted when the NDL gate evaluates.