The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2006
Filed:
Mar. 26, 2002
Applicants:
Peter Hazucha, Beaverton, OR (US);
Atila Alvandpour, Portland, OR (US);
Ram Krishnamurthy, Portland, OR (US);
Tanay Karnik, Portland, OR (US);
Inventors:
Peter Hazucha, Beaverton, OR (US);
Atila Alvandpour, Portland, OR (US);
Ram Krishnamurthy, Portland, OR (US);
Tanay Karnik, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/096 (2006.01);
U.S. Cl.
CPC ...
Abstract
A dynamic logic gate with a conditional keeper, the conditional keeper comprising a pMOSFET pull-up that switches ON only after the dynamic logic gate completes an evaluation so as to avoid contention with the pull-down network. By sizing the conditional keeper to be stronger than the half-keeper, embodiments may realize a significant reduction in soft error rates that are latched.