The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2006
Filed:
Apr. 01, 2005
Chiahua Ho, Hsinchu, TW;
Yen-hao Shih, Hsinchu, TW;
Hsiang-lan Lung, Hsinchu, TW;
Shih-ping Hong, Hsinchu, TW;
Shih-chin Lee, Hsinchu, TW;
ChiaHua Ho, Hsinchu, TW;
Yen-Hao Shih, Hsinchu, TW;
Hsiang-Lan Lung, Hsinchu, TW;
Shih-Ping Hong, Hsinchu, TW;
Shih-Chin Lee, Hsinchu, TW;
MACRONIX International Co., Ltd., Hsinchu, TW;
Abstract
An one-time programmable read only memory is provided. An N-type doping region and a first P-type doping layer are disposed in a P-type semiconductor substrate sequentially. A second P-type doping layer is disposed between the first P-type doping layer and the N-type doping region. The second P-type doping layer with higher doping level, which has a linear structure, is served as a bit line. An electrically conductive layer is disposed over the P-type semiconductor substrate. The electrically conductive layer also has a linear structure that crosses over the first P-type doping layer. The first N-type doping layer is disposed in the P-type semiconductor substrate between the electrically conductive layer and the first P-type doping layer. The arrangement of N-type and P-type doping layer is used to be selective diode device. An anti-fuse layer is disposed between the electrically conductive layer and the first N-type doping layer.