The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2006

Filed:

Mar. 12, 2004
Applicant:

Joerg Radecker, Dresden, DE;

Inventor:

Joerg Radecker, Dresden, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

In order to produce insulator structures (), insulator trenches () with aspect ratios of greater than 4:1 are introduced into a semiconductor substrate () from a substrate surface () and filled with an insulator filling (). The insulator filling () is formed from a plurality of portions () which are deposited successively in situ in an HDP/CVD process chamber in the course of an HDP/CVD deposition process. A main layer () is provided made from fluorine-doped silicon oxide with good filling properties. A barrier layer () is formed directly before the deposition of the main layer (), said barrier layer preventing an outgassing of the fluorine from the fluorine-doped silicon oxide (), an interaction of the fluorine with the semiconductor substrate () and a formation of defect areas () with oxide of low quality in the area of the insulator filling (). The barrier () makes it possible to form nondegrading p-channel transistors () in the area of the substrate surface (). An additional layer () and a termination layer () respectively effect an adaptation and linking of the main layer () and of the barrier layer () to preceeding and succeeding process steps.


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