The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2006

Filed:

Jun. 02, 2003
Applicants:

Leah M. Miller, Fremont, CA (US);

Farshad Ghahghahi, Los Gatos, CA (US);

Inventors:

Leah M. Miller, Fremont, CA (US);

Farshad Ghahghahi, Los Gatos, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for designing a routing pattern for electrical contacts on a printed circuit board by arranging contacts in an array of rows and columns on the printed circuit board, connecting groups of n columns of contacts to n−1 columns of vias disposed interstitially between the contacts, thereby forming a vertical channel that does not extend completely through the contact array. Connecting the vias to traces, and routing the traces to an outside edge of the via array through the vertical channel. Connecting groups of n rows of the contacts to n−1 rows of vias disposed interstitially between the contacts, thereby forming a horizontal channel that does not extend completely through the contact array, and intersects with the vertical channel. Connecting the vias to traces, and routing the traces to the outside edge of the via array through the horizontal channel.


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