The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2006
Filed:
Mar. 28, 2001
Hong Wang, Fremont, CA (US);
Christopher J. Hughes, Urbana, IL (US);
Ralph Kling, Sunnyvale, CA (US);
Yong-fong Lee, San Jose, CA (US);
Daniel M. Lavery, Santa Clara, CA (US);
John Shen, San Jose, CA (US);
Jamison Collins, Los Gatos, CA (US);
Hong Wang, Fremont, CA (US);
Christopher J. Hughes, Urbana, IL (US);
Ralph Kling, Sunnyvale, CA (US);
Yong-Fong Lee, San Jose, CA (US);
Daniel M. Lavery, Santa Clara, CA (US);
John Shen, San Jose, CA (US);
Jamison Collins, Los Gatos, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Instruction-level parallelism in software pipelined loops is exploited by predicting future register rotations. A processor includes an architected current frame marker register and at least one unarchitected frame marker register. Register rotation prediction is achieved by setting the register rotation of future iterations of a software loop to be a function of the unarchitected frame marker registers. True data dependencies remain, but the dependencies caused solely by register renaming are removed. Dynamic predication is used to predicate instructions from future iterations, allowing them to be squashed if dependencies are later found. The register renaming that results from the prediction can be included in instructions in a buffer, or a renaming stage in an execution pipeline can perform the renaming.