The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 2006
Filed:
Apr. 23, 2003
Manu Chopra, New Delhi, IN;
Xiaoqun Du, New Providence, NJ (US);
Ronald H. Hardin, Pataskala, OH (US);
Alok Jain, New Delhi, IN;
Robert P. Kurshan, New York, NY (US);
Pratik Mahajan, New Delhi, IN;
Ravi Prakash, Noida, IN;
Kavita Ravi, Chatham, NJ (US);
Manu Chopra, New Delhi, IN;
Xiaoqun Du, New Providence, NJ (US);
Ronald H. Hardin, Pataskala, OH (US);
Alok Jain, New Delhi, IN;
Robert P. Kurshan, New York, NY (US);
Pratik Mahajan, New Delhi, IN;
Ravi Prakash, Noida, IN;
Kavita Ravi, Chatham, NJ (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method and system for verifying integrated circuit designs through partitioning. In an embodiment, a design is partitioned, then each partition is verified. In one embodiment, the design is partitioned at the granularity of modules. In another embodiment, the design is partitioned at the granularity of instances. In a third embodiment, instances are grouped together, subject to a weight threshold, so as to form possibly overlapping partitions of instances that are contiguous in the design hierarchy, with the purpose of avoiding, to the extent possible, false negatives. In a further embodiment, the design is partitioned to avoid redundant partitions. In an embodiment, model checking is applied to one or more local properties in each partition. In another embodiment, simulation is used to verify each partition.