Nonvolatile memories with asymmetric transistors, nonvolatile memories with high voltage lines extending in the column direction, and nonvolatile memories with decoding circuits sharing a common area

Abstract

Nonvolatile memory cells () are connected to a bitline (BL). The bitline is also connected to a source/drain region () of a transistor (), a Y multiplexer transistor for example. This source/drain region is exposed to a higher voltage, and hence is made to have a higher junction breakdown voltage, than the other source/drain region () of the same transistor. A nonvolatile memory has a plurality of memory arrays (), a global decoder () and secondary decoders (). The selection signals provided by the global decoder to the secondary decoders for selecting the control gate lines () and the source lines () are carried by lines () running in the row direction. These signals are low voltage signals (between 0V and Vcc). The super high voltages are carried by lines () extending in the column direction to reduce noise injection into the control gate lines, source lines, and wordlines (), and to reduce the parasitic capacitance associated with the super high voltage lines. An integrated circuit has at least two memory arrays () with control gate lines (), source lines (), and wordlines (). A global decoder () and secondary decoders () select the control gate lines and the source lines. Each secondary decoder is located in an area spaced from the arrays. The control gate line and source line decoding circuits in each secondary decoder share a common area to reduce the memory size. Other features are also provided.