The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 2006
Filed:
Mar. 20, 2003
Method for scalable architectures in stackable three-dimensional integrated circuits and electronics
Raymond Jit-hung Sung, Wilmington, MA (US);
Tyler Lee Brandon, Sherwood Park, AB, CA;
John Conrad Koob, Edmonton, AB, CA;
Duncan George Elliott, Edmonton, AB, CA;
Daniel Arie Leder, Spruce Grove, AB, CA;
Raymond Jit-Hung Sung, Wilmington, MA (US);
Tyler Lee Brandon, Sherwood Park, AB, CA;
John Conrad Koob, Edmonton, AB, CA;
Duncan George Elliott, Edmonton, AB, CA;
Daniel Arie Leder, Spruce Grove, AB, CA;
Other;
Abstract
The design methods described enable three-dimensional integrated circuit systems in which all of the dies, in a vertically bonded stack of dies, are identical. Only one mask set and wafer type is required since a single circuit design is produced for one die in the stack and reused for all the dies with little or no modification. The system scales directly as the level of stacking is increased while incurring no extra design effort, beyond that required for the initial design.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile