The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2006

Filed:

Jul. 20, 2001
Applicants:

Masaki Hirase, Gifu-ken, JP;

Satoru Shimada, Gifu-ken, JP;

Inventors:

Masaki Hirase, Gifu-ken, JP;

Satoru Shimada, Gifu-ken, JP;

Assignee:

Sanyo Electric Co., Ltd., Moriguchi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a semiconductor substrate including a mask aligning trench. The method includes forming the mask aligning trench and an element partitioning trench. The element partitioning and mask aligning trenches are filled with insulation. The insulation in the element partitioning trench is masked and the insulation in the mask aligning trench is etched. As a result, a residue of the insulation in the mask aligning trench is below the upper edge of the mask aligning trench. The mask aligning trench is easily detected. Thus, positioning a patterning mask on the substrate can be performed accurately.


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Hirase, Masaki. (2006). Semiconductor device and method for manufacturing the same (U.S. Patent No. 7045434). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7045434

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