The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2006
Filed:
Feb. 18, 2004
Miles G. Canada, Colchester, VT (US);
Stephen F. Geissler, Underhill, VT (US);
Robert M. Houle, Williston, VT (US);
Dongho Lee, Poughkeepsie, NY (US);
Vinod Ramadurai, South Burlington, VT (US);
Mathew I. Ringler, Burlington, VT (US);
Gerard M. Salem, Essex Junction, VT (US);
Timothy J. Vonreyn, Williston, VT (US);
Miles G. Canada, Colchester, VT (US);
Stephen F. Geissler, Underhill, VT (US);
Robert M. Houle, Williston, VT (US);
Dongho Lee, Poughkeepsie, NY (US);
Vinod Ramadurai, South Burlington, VT (US);
Mathew I. Ringler, Burlington, VT (US);
Gerard M. Salem, Essex Junction, VT (US);
Timothy J. Vonreyn, Williston, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and circuit for adjusting the read margin of a self-timed memory array. The electronic circuit, including: a memory cell array including a sense amplifier self-timed decode circuit adapted to set a base read time delay of the memory cell array; and a read delay adjustment circuit coupled to the memory cell array, the read delay adjustment circuit adapted to adjust the base read time delay of the memory array based on an operating frequency of the memory cell array.