The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 2006
Filed:
Feb. 11, 2004
Sunil Talwar, Warwickshire, GB;
Dmitriy Rumynin, Coventry, GB;
Peter Meulemans, Coventry, GB;
Arithmatica Limited, , GB;
Abstract
Logic circuit generating four binary outputs as four threshold functions of four binary inputs, including: first, second, third, and fourth threshold functions which are respectively high if at least one, two, three and all of the binary inputs are high; first logic having two logic parts that each include NOR and NAND gates, and having two first-level inputs for receiving the binary inputs and two first-level outputs; and second logic having four second-level outputs, four second-level inputs for receiving second-level binary inputs and connected to the four first-level outputs, NAND gate, first gate generating logical OR combinations and NAND combining the logical OR combination with two other second-level binary inputs, a second gate generating logical OR combinations of two pairs of second-level binary inputs and NAND combining the logical OR combinations, and a NOR gate; wherein one of four binary outputs is generated at each of the four outputs.