The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7039573 B1

PDF
Full Text
Expired
Date of Patent:
May. 02, 2006

Filed:

Oct. 05, 2001
Applicant:

Michio Komoda, Tokyo, JP;

Inventor:

Michio Komoda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 17/10 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

The total resistance value of a coupling portion between first and second circuits is used as the resistance value of a load model; one-half of the total capacity value of the coupling portion is used as each coupling capacity value of the load model; the sum of one-half of the total earth capacity value of the coupling portion and the total capacity value of a non-coupling portion near a first circuit driver is used as the earth capacity value of the load model at a point near the first circuit driver; and the sum of one-half of the total earth capacity value of the coupling portion and the total capacity value of a non-coupling portion farther from the first circuit driver than the coupling portion is used as the earth capacity value of the load model at a point remote from the first circuit driver.


Find Patent Forward Citations

Komoda, Michio. (2006). Method of formulating load model for glitch analysis and recording medium with the method recorded thereon (U.S. Patent No. 7039573). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7039573

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