The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2006
Filed:
Sep. 12, 2003
Satwant Singh, Fremont, CA (US);
Cyrus Tsui, Los Altos, CA (US);
Satwant Singh, Fremont, CA (US);
Cyrus Tsui, Los Altos, CA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
An ASIC conversion of a programmable logic device (PLD) is provided. The PLD includes a plurality of logic blocks coupled together by a PLD routing structure. The ASIC includes a plurality of logic blocks corresponding on a one-to-one basis with logic blocks in the PLD and a routing structure corresponding to the programmable routing structure of the PLD. Vias or traces are selectively placed in the ASIC so that logical behavior of its logic blocks matches that implemented in the PLD and the signal propagation delay through the ASIC matches the delay through the PLD.