The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 2006
Filed:
Jul. 29, 2004
Applicants:
Stephan Grunow, Dallas, TX (US);
Satyavolu Srinivas Papa Rao, Garland, TX (US);
Noel M. Russell, Plano, TX (US);
Inventors:
Stephan Grunow, Dallas, TX (US);
Satyavolu Srinivas Papa Rao, Garland, TX (US);
Noel M. Russell, Plano, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method for fabricating a seed layer. A seed layer () is deposited over a barrier layer () using a three-step process comprising a low AC bias power step, a high AC bias power step, and a lower/zero AC bias power step. The low AC bias power step provides low overhang. The high AC bias power step provides good sidewall coverage. The lower/zero AC bias step recovers areas exposed by re-sputtering during the high AC bias power step.